1. Field of the Invention
The invention relates to a method of manufacture of a semiconductor device employing silicide.
2. Description of the Related Art
As the dimensions of semiconductor devices are scaled down, fine patterning on the surface of a semiconductor substrate (the dimensions of gates of transistors, the width of device isolation regions, the width of interconnect lines, etc.) is increasingly required. Further, it is required to reduce the dimensions in the direction perpendicular to the surface of the semiconductor substrate (the diffusion layers of source/drain and extension regions and the depth of junctions of the source/drain and extension regions).
However, simply trying to reduce the vertical dimensions results in problems of degradation of the performance of transistors. For example, when the resistivity of extension regions increases and consequently the parasitic resistance increases, the driving capability of transistors degrades. In order to implement shallow extension regions of low resistivity, a thermal processing method has been developed which suppresses the diffusion of impurity ions implanted at high concentration.
In addition, it is also required to reduce the parasitic resistance of source/drain regions by forming a silicide film of low resistivity on their contact regions. To form a silicide film of low resistivity, a self-aligned silicide (salicide) process is used (see, for example, U.S. Pat. No. 6,806,172).
For example, in manufacturing a metal oxide semiconductor (MOS) field effect transistor using that salicide process, a semiconductor substrate of silicon is first formed with device isolation regions of insulating layers and gate electrodes having a sidewall insulating film. Then, impurity diffusion layers of source/drain regions are formed in portions of the semiconductor substrate between the device isolation regions and the sidewall insulating film by means of ion implantation.
Next, a film of metal, such as Ni, is deposited onto the surface of the semiconductor substrate formed with the impurity diffusion layers. A film of metal silicide, such as nickel silicide (NiSi), is then formed on the surface of the polysilicon gate electrodes and the surface of the impurity diffusion layers by means of rapid thermal annealing (RTA) using a halogen lamp or furnace annealing using an electric furnace. Unreacted metal film on the insulating film on the device isolation regions and the sidewall insulating film is removed. Thus, a MOSFET is manufactured.
As the dimensions of devices are scaled down, the pn junctions of the source/drain regions become shallower. For this reason, the distance between the bottom of the metal silicide film formed on the surface of the impurity diffusion layer and the pn junction of the impurity diffusion layer is reduced. A problem arises in that the frequency of occurrence of a failure of junction leakage increases because an electric field concentrates at protruding portions of the bottom of the metal silicide film and the metal for silicide formation is made easy to diffuse to the pn junction by a thermal process after silicidation.
The RTA is larger in the rate of temperature elevation than the furnace annealing and hence allows heating to be carried out in a shorter time. Thus, the RTA allows a thin film of metal silicide to be formed with the diffusion of metal suppressed.
However, the RTA for silicide formation causes the metal film deposited on the insulating film on the device isolation regions and the sidewall insulating film of the gate electrode to aggregate and flow into the source/drain regions and the gate electrode. As a result, the thickness of the metal silicide film at the edges of the source/drain regions and the edges of the gate electrode increases above a design value, which leads to increased junction leakage.